The AI Designing AI Chips Still Has to Pass Physics
OpenAI and Synopsys have built a frontier model that operates chip design software autonomously. It cannot override the laws of physics, and the companies say that is the point.
OpenAI and Synopsys announced on September 30, 2026, a multi-year partnership to develop GPT-Synopsys, a specialized AI model trained to run Synopsys electronic design automation tools directly. The deal restructures what AI assistance in chip design looks like. Instead of a general-purpose model answering questions about a workflow, a purpose-trained model executes the workflow. Early technology engagements are underway with unnamed semiconductor customers.
The financial terms, reported by Reuters, are unusual by industry standards. OpenAI pays Synopsys a training subscription fee to learn the tools. When customers use the product, the two companies share revenue based on how well the model demonstrably improves a chip design. Whether "improvement" is measured in power reduction, performance gain, area savings, or some combination has not been publicly defined.
What EDA Is, and Where the Hours Go
Electronic design automation is the software stack that turns an engineer's logical description of a circuit into a physical blueprint a semiconductor fab can manufacture. The steps are numerous and interdependent.
A chip design begins as something close to code, a register-transfer-level description of what the logic should do. EDA tools translate that description into a layout of billions of transistors on silicon, arranged to hit targets for power draw, processing speed, and die area. These three constraints, known collectively as PPA (power, performance, area), have to be balanced against each other throughout the process.
After layout comes timing closure: verifying that signals move through the chip fast enough to meet clock frequencies without setup or hold violations. Then verification closure: confirming that the physical design still does what the original specification required. Finally, sign-off, where the layout is checked against the actual physics and manufacturing rules of the fabrication process. A chip that passes sign-off can be sent to the fab. One that does not goes back for more iterations.
Each of these phases involves running tools, reading outputs, adjusting parameters, running the tools again, and repeating until results converge. The iteration cycles are where engineering time goes. A senior chip designer can spend weeks or months on timing closure alone for a complex design.
From Assistant to Operator
Until now, the role of AI in EDA has been advisory. General-purpose models can answer questions, explain tool options, or suggest parameter adjustments, but a human runs the commands. The claimed advance in GPT-Synopsys is that the model becomes the operator.
According to the companies, engineers using GPT-Synopsys delegate objectives rather than tasks. An engineer specifies a PPA target, a timing budget, or a verification milestone. The model then runs Synopsys tools, reads the outputs, decides what to adjust, makes the changes, and reruns the tools, iterating toward a verified outcome that the engineer can review. The human moves from running the loop to setting the goal and reviewing the result.
Greg Brockman described the ambition in the joint press release: "We're using our most advanced technology to improve the systems that power AI." He added separately, via Reuters, that the model could shave weeks and months from the design process. Synopsys CEO Sassine Ghazi put it this way: "The future of semiconductor engineering requires dramatic acceleration of the chip design process without compromising PPA or first-time-right silicon."
Both statements are company claims. No independent benchmark of GPT-Synopsys performance has been published. The unnamed early customers have not released results.
The Agent Loop in Practice
GPT-Synopsys runs on OpenAI-hosted infrastructure. It interoperates with customer agent harness systems, the software scaffolding that manages tool calls, data flows, and human review checkpoints. It also integrates with Synopsys.ai and the Synopsys Autopilot platform, which already handles some automation in the Synopsys tool suite.
The agent loop works approximately as follows. An engineer loads a design and sets objectives. The model calls Synopsys tools, receives structured outputs (timing reports, power estimates, area summaries, violation lists), interprets those outputs, and formulates a next action. It implements the change, reruns relevant tools, compares the new outputs to the target, and continues until it reaches a stopping condition or hands control back to the engineer. The engineer reviews the converged design before it moves forward in the flow.
Customer design data is not used to train the model, according to the companies. Data is encrypted at rest and in transit. Configurable retention, audit, and permission controls are available. For chip companies, whose design IP is among the most valuable assets they hold, those terms matter as much as the capability claims.
The Physics Guardrail
"The model needs these guardrails in order to check the physics." – Sassine Ghazi, Synopsys CEO
The line that matters most in the Reuters coverage came from Ghazi, who was direct about what the model cannot do on its own: "The model needs these guardrails in order to check the physics." The guardrails he described are Synopsys's own traditional verification tools, which remain in the loop to double-check model output. Physical sign-off, the final check against fabrication rules, remains what Ghazi called the "ground truth."
This is not a limitation the companies are trying to minimize. It reflects something real about chip design. The fabrication rules that sign-off tools enforce are not heuristics. They encode the actual physics of how materials behave at nanometer scales. A model that has learned to operate EDA tools can optimize toward targets, but confirming that a layout will actually work in silicon requires running deterministic physics-based checks. Those checks do not change because the upstream work was done by a model.
The practical structure is: AI handles the iteration, physics handles the validation, and humans set the objectives and review the outcomes. Whether that structure will hold as the technology matures, or whether it represents a durable division of labor, is not yet answerable.
The Money, and Why It Follows Measured Improvement
The revenue-share structure is worth examining because of what it requires. A fee for tool access is standard licensing. Revenue shared on the basis of demonstrated improvement is not. For that arrangement to function, improvement has to be measurable at the end of a completed engagement.
In EDA, measurement is feasible. PPA results are quantified. Timing closure either passes or it does not. Sign-off either passes or it does not. If two designs go through the same flow, one with GPT-Synopsys and one without, the outputs are comparable. The companies have not disclosed how the improvement calculation is defined or audited, but the domain does produce the kind of objective outputs the structure implies.
Ghazi told Reuters the deal was structured not to cannibalize Synopsys's existing business. The revenue-share model, if it pays out on real improvements rather than usage volume, creates an incentive for the model to actually improve designs rather than merely accelerate tool calls that produce the same result faster.
Synopsys raised its fiscal 2027 revenue growth expectation to 15 percent against analyst consensus of 11.19 percent (per LSEG data cited by Reuters). Synopsys shares rose as much as 7 percent after the announcement. The market read was that this adds to Synopsys revenue rather than redistributing it.
What Has Not Been Established
Several things the companies have said may well turn out to be accurate. None of them has been independently verified.
No third-party benchmark of GPT-Synopsys improvement on real design tasks has been published. All capability claims originate from OpenAI and Synopsys. The early semiconductor customers are unnamed and have not published results. The specific metric defining the revenue-share "improvement" is not publicly disclosed. Human engineer review of converged designs remains required, as does physics sign-off.
These are normal conditions for an early-stage commercial AI product. They are worth stating plainly because the framing around the announcement runs ahead of the evidence.
Practical Takeaway
For chip teams evaluating AI tooling, GPT-Synopsys represents a structural shift worth tracking even if the current capability claims cannot yet be verified. The move from advisory AI to operative AI in EDA changes what engineers spend time on, not just how fast certain tasks complete. If the model reliably handles iteration loops, the scarce resource becomes engineering judgment, which is where it arguably should be.
For AI tool buyers more broadly, the revenue-share structure is worth noting as a model. Payment tied to demonstrated, domain-verifiable improvement is a more auditable arrangement than capability claims in marketing materials. Whether that structure becomes common in enterprise AI deployment will depend on how well it holds up when the improvement metrics are tested against real engagements.
The AI designing AI chips still has to pass physics. For now, so does everything else.
Sources and further reading
https://news.synopsys.com/2026-09-30-OpenAI-and-Synopsys-Announce-GPT-Synopsys-Frontier-Intelligence-to-Revolutionize-Chip-Design
https://www.reuters.com/business/synopsys-openai-strike-deal-develop-ai-model-chip-design-work-2026-09-30/
https://www.engineering.com/synopsys-and-openai-partner-on-semiconductor-design-ai/
